Non-volatile memory device and erase and read methods thereof

ABSTRACT

An erase method of a non-volatile memory device includes first erasing memory cells of a non-volatile memory device with a first erase voltage; in response to a judgment that the erasure of at least one of the memory cells has failed, determining an amount of voltage to add to the first erase voltage, the amount being based on a threshold voltage distribution of the first erased memory cells; and second erasing the memory cells with a second erase voltage, the second erase voltage being higher than the first erase voltage by the determined amount.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2009-0016872 filed onFeb. 27, 2009, the disclosure of which is incorporated by referenceherein in its entirety.

BACKGROUND

1. Technical Field

The present inventive concept relates to a semiconductor memory device,and more particularly, to a non-volatile memory device.

2. Discussion of Related Art

Non-volatile memory devices may include flash memory devices andresistance-variable memory devices, for example. Flash memory devicesmay be classified into NAND flash memory devices and NOR flash memorydevices. NOR flash memory devices include memory cells that areindependently connected with bit lines and word lines and have fastrandom access times. NAND flash memory devices include a plurality ofmemory cells that are connected in series so that only one contact perstring is necessary. Accordingly, NAND flash memory devices have a highdegree of integration.

To increase the integration of a flash memory device, developments havebeen made on a multi-bit cell that is capable of storing a plurality ofdata bits in one memory cell. Such a memory cell is called a multi-levelcell (MLC) or multi-bit cell. A memory cell that is capable of storingone data bit is called a single-level cell (SLC) or single-bit cell.Generally, data bits of a multi-level cell may be programmed to belongto one of two or more threshold voltage distributions. Programming maystress a multi-level cell and cause its threshold voltage distributionsto overlap, thus potentially leading to erase and/or read errors.Accordingly, there is a need to reduce cell stress in a nonvolatilememory device.

SUMMARY

An exemplary embodiment of the inventive concept provides an erasemethod of a non-volatile memory device, which comprises first erasingmemory cells of a non-volatile memory device with a first erase voltage;in response to a judgment that the first erasure of at least one of thememory cells has failed, determining an amount of voltage to add to thefirst erase voltage, the amount being based on a threshold voltagedistribution of the first erased memory cells; and second erasing thememory cells with a second erase voltage, the second erase voltage beinghigher than the first erase voltage by the determined amount.

The amount to add to the first erase voltage is determined by searchingfor a maximum upper voltage of the threshold voltage distribution of thefirst erased memory cells that is less than a verification-read voltage.

The maximum upper voltage is searched for by iteratively performing averification-read operation.

The erasure of the selected memory cells is terminated by applying thesecond erase voltage to the memory cells.

The memory cells to be erased are selected.

The memory cells comprise a multi-level cell.

An exemplary embodiment of the inventive concept provides an erasemethod of a non-volatile memory device, which comprises first erasingmemory cells of a non-volatile memory device with a first erase voltage;in response to a judgment that the first erasure of at least one of thememory cells has failed: a) performing a verification operation with afirst verification-read voltage; b) obtaining an offset value by usingthe first verification-read voltage; c) increasing or decreasing thefirst verification-read voltage by the offset value to generate a newverification-read voltage, based on a result of the verificationoperation; and d) determining whether the offset value is less than orequal to a reference voltage; and in response to the offset value beingless than or equal to the reference voltage, second erasing the memorycells with a second erase voltage obtained by adding the newverification-read voltage to the first erase voltage; otherwise,repeating a-d with each newly generated verification-read voltage as thefirst verification-read voltage until the offset value is less than orequal to the reference voltage, and then, performing the second erasureof the memory cells.

The verification operation is judged to have passed in response to thefirst verification-read voltage being higher than a maximum uppervoltage of a threshold voltage distribution of the first erased memorycells.

In response to the judgment that the verification operation has passed,the new verification-read voltage is obtained by subtracting the offsetvalue from the first verification-read voltage.

The verification operation is judged to have failed in response to thefirst verification-read voltage being less than a maximum upper voltageof a threshold voltage distribution of the first erased memory cells.

In response to the judgment that the verification operation has failed,the new verification-read voltage is obtained by adding the offset valueto the first verification-read voltage.

The first erasure of at least one of the memory cells is judged to havefailed in response to a maximum upper voltage of a threshold voltagedistribution of the first erased memory cells being higher than apredetermined verification-read voltage.

The predetermined verification-read voltage is 0V.

The second erase voltage is less than the predeterminedverification-read voltage.

The offset value is obtained by dividing the first verification-readvoltage by a number more than one.

An exemplary embodiment of the inventive concept provides a read methodof a non-volatile memory device, which comprises first reading memorycells of a non-volatile memory device with a first read voltage; inresponse to a judgment that the first reading of at least one of thememory cells is uncorrectable: a) performing a verification operationwith a first read verification voltage; b) obtaining an offset voltageby using the first read verification voltage; c) increasing ordecreasing the first read verification voltage by the offset voltage togenerate a new read verification voltage, according to a result of theverification operation; and d) determining whether the offset value isless than or equal to a reference voltage; and in response to the offsetvalue being less than or equal to the reference voltage, second readingthe memory cells with a second read voltage obtained by adding the newread verification voltage to the first read voltage; otherwise,repeating a-d with each newly generated read verification voltage as thefirst read verification voltage until the offset value is less than orequal to the reference voltage, and then, performing the second readingof the memory cells.

An error checking and correction (ECC) algorithm determines that thereading of at least one of the memory cells is uncorrectable.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present inventive concept willbecome more apparent by describing in detail exemplary embodimentsthereof with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a non-volatile memory device accordingto an exemplary embodiment of the inventive concept.

FIG. 2 is a flowchart for describing an erase operation of anon-volatile memory device according to an exemplary embodiment of theinventive concept.

FIGS. 3 to 6 are diagrams showing variations of threshold voltagedistributions in an erase operation according to an exemplary embodimentof the inventive concept.

FIG. 7 is a flowchart for describing an erase operation of anon-volatile memory device according to an exemplary embodiment of theinventive concept.

FIG. 8 is a flowchart for describing an erase voltage searching processin FIG. 7.

FIGS. 9 to 12 are diagrams showing threshold voltage distributions in anerase operation according to an exemplary embodiment of the inventiveconcept.

FIG. 13 is a block diagram showing a computing system including a flashmemory device according to an exemplary embodiment of the inventiveconcept.

FIG. 14 is a block diagram showing a memory-based storage deviceaccording to an exemplary embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will now be described indetail with reference to the accompanying drawings. The inventiveconcept may, however, be embodied in many different forms and should notbe construed as limited to the exemplary embodiments set forth herein.Like reference numerals in the drawings may refer to like elements.

FIG. 1 is a block diagram showing a non-volatile memory device accordingto an exemplary embodiment of the inventive concept.

Referring to FIG. 1, a non-volatile memory device 100 according to anexemplary embodiment of the inventive concept may be a flash memorydevice. The non-volatile memory device 100 may be applied to all memorydevices which generate interference between memory cells due tointegration.

The non-volatile memory device 100 may include a memory cell array 110which stores M-bit data information (M being an integer of 1 or more).The memory cell array 110 may be divided into a plurality of areas,which include a data area for storing user data and a spare area. But,the areas of the memory cell array 110 are not limited thereto. Theareas of the memory cell array 110 may be formed of a plurality ofmemory blocks, respectively. A memory block structure is well known toone skilled in the art, and a description thereof is thus omitted. Forexample, an exemplary array structure is disclosed in commonly assignedU.S. Pat. No. 6,285,587, entitled “MEMORY CELL STRING STRUCTURE OF AFLASH MEMORY DEVICE”, the disclosure of which is incorporated byreference herein in its entirety.

The non-volatile memory device 100 may further comprise a page buffercircuit 120, a decoder circuit 130, a voltage generator circuit 140,control logic 150, and an input/output buffer circuit 170.

The page buffer circuit 120 may be configured to read data from orprogram data in the memory cell array 110 in response to the control ofthe control logic 150. The decoder circuit 130 may operate in responseto the control logic 150. The decoder circuit 130 may be configured toselect a memory block of the memory cell array 110 and a word line ofthe selected memory block. The selected word line may be driven with aword line voltage from the voltage generator circuit 140. The voltagegenerator circuit 140 may be controlled by the control logic 150 andconfigured to generate word line voltages (for example, a read voltage,a program voltage, a pass voltage, a local voltage, and a verificationvoltage) to be supplied to the memory cell array 110.

The control logic 150 may control an overall operation of thenon-volatile memory device 100 and include a pass/fail checker 160. Thepass/fail checker 160 may be configured to check program/erase pass/failwith respect to data read out by the page buffer circuit 120 in awired-OR manner or a Y-scan manner. In the wired-OR manner, read databits may be reflected on a wire at the same time, and the pass/failchecker 160 may judge program/erase pass/fail based on a logic level ofthe wire. In the Y-scan manner, read data bits may be providediteratively by a given unit to the pass/fail checker 160 via a columnselector which, although not shown, may be included in the input/outputbuffer circuit 170. The input/output buffer circuit 170 may beconfigured to transfer data from an external device (for example, amemory controller) to the page buffer circuit 120 or data from the pagebuffer circuit 120 to the external device.

The non-volatile memory device 100 may be configured to operate inresponse to a request from an external device such as a memorycontroller (not shown). Although not shown in the drawings, the memorycontroller may include a processing unit such as a central processingunit (CPU) or microprocessor, an error checking and correction (ECC)engine, and a buffer memory, for example.

An iterative erase operation may stress non-volatile memory cells. Hothole injection (HHI) may arise in stressed memory cells. The HHI maymake a threshold voltage of a memory cell increase. This may cause ascan fail such that an erased memory cell is judged not to be erased.The stress to memory cells may be reduced by lowering an erase voltage.This may cause incompletely erased memory cells.

The non-volatile memory device 100 according to an exemplary embodimentof the inventive concept may be configured to search for a maximum uppervoltage of a threshold voltage distribution after first erasing memorycells and to decide a next erase voltage based on the search result.Memory cells may be completely erased by an erase voltage thus decided.In this process, which will be more fully described hereinafter, anerase voltage is applied to memory cells twice. Accordingly, it ispossible to reduce the stress to memory cells to be erased.

FIG. 2 is a flowchart for describing an erase operation of anon-volatile memory device according to an exemplary embodiment of theinventive concept. An erase operation of a non-volatile memory deviceaccording to an exemplary embodiment of the inventive concept will bemore fully described with reference to the accompanying drawings.

In step S11, a non-volatile memory device 100 may execute an eraseoperation based on an initial erase voltage Ve. Here, the initial erasevoltage Ve is 18V. The erase voltage Ve may be applied to a bulk (orsubstrate) on which memory cells are formed. In step S12, thenon-volatile memory device 100 may execute a verification-readoperation. During the verification-read operation, a verificationvoltage of 0V may be applied to erased memory cells. In step S13, thenon-volatile memory device 100 may judge whether an erase operation haspassed or failed. If the erase operation has passed, the erase operationmay be ended. If the erase operation has failed, the procedure goes tostep S14, in which the erase voltage Ve is increased by an increment ΔV.Afterward, the steps S11 to S14 may be repeated until the eraseoperation has passed.

FIGS. 3 to 6 are diagrams showing variations of threshold voltagedistributions in an erase operation according to an exemplary embodimentof the inventive concept.

In FIG. 3, there is illustrated a threshold voltage distribution ST oferased memory cells after an erase operation is executed based on aninitial erase voltage Ve. As understood from FIG. 3, an erase operationmay not be ended even though memory cells are erased in step S11. Thisis so, because a maximum upper voltage of the threshold voltagedistribution ST may be placed over 0V, for example, at about 1.1V higherthan a verification-read voltage of 0V. This means that the eraseoperation is to be performed again with an erase voltage being increasedby ΔV. Here, ΔV may be 0.5V.

In FIG. 4, there is illustrated a threshold voltage distribution ST oferased memory cells after an erase operation is executed based on anerase voltage Ve increased by ΔV (0.5V). As illustrated in FIG. 4, amaximum upper voltage of the threshold voltage distribution ST may beplaced at about 0.6V higher than the verification-read voltage of 0V.This means that the erase operation is to be performed again with anerase voltage being increased by ΔV.

In FIG. 5, there is illustrated a threshold voltage distribution ST oferased memory cells after an erase operation is executed based on anerase voltage Ve increased by 2ΔV (1.0V). As illustrated in FIG. 5, amaximum upper voltage of the threshold voltage distribution ST may beplaced at about 0.1V higher than the verification-read voltage of 0V.This means that the erase operation is to be carried out again with anerase voltage being increased by ΔV.

In FIG. 6, there is illustrated a threshold voltage distribution ST oferased memory cells after an erase operation is executed based on anerase voltage Ve increased by 3ΔV (1.5V). As illustrated in FIG. 6, amaximum upper voltage of the threshold voltage distribution ST may beplaced below about 0V. This means that the erase operation has passed.Accordingly, the erase operation may be ended.

FIG. 7 is a flowchart for describing an erase operation of anon-volatile memory device according to an exemplary embodiment of theinventive concept. FIG. 8 is a flowchart for describing an erase voltagesearching process in FIG. 7. Below, an erase operation of a non-volatilememory device according to an exemplary embodiment of the inventiveconcept will be more fully described with reference to the accompanyingdrawings.

In step S21, a non-volatile memory device 100 may execute an eraseoperation based on an erase voltage Ve. In step S22, the non-volatilememory device 100 may execute a verification-read operation. During theverification-read operation, a verification voltage of 0V may be appliedto erased memory cells. In step S23, the non-volatile memory device 100may judge whether an erase operation has passed or failed. If the eraseoperation is judged to have passed, the erase operation may be ended. Ifthe erase operation is judged to have failed, the procedure goes to stepS24, in which there is executed an operation of deciding the erasevoltage Ve. In the deciding operation, the erase voltage Ve may beincreased not by a fixed increment ΔV (for example, 0.5V), but by anewly decided increment higher or lower than the fixed increment ΔV.This will be more fully described with reference to FIG. 8. Afterdeciding the erase voltage Ve, the procedure goes to step S21.

The erase voltage deciding operation may be performed to decide anincrement which to increase an erase voltage. This may be accomplishedby searching for a maximum upper voltage of a threshold voltagedistribution of erased memory cells in a binary search manner. An erasevoltage for next erasing may be decided based on the found maximum uppervoltage. This may be executed as follows.

First, in step S241, the non-volatile memory device 100 may execute afirst verification-read operation based on a verification-read voltageVvfy. In an exemplary embodiment, the maximum verification-read voltageVvfy may be set to about 1.6V. But, the maximum verification-readvoltage may not be limited thereto. In step S242, an offset value V_(OS)may be determined by dividing the maximum verification-read voltage Vvfyby 2. The offset value V_(OS) may be used to terminate an operation ofsearching for a maximum upper voltage of a threshold voltagedistribution of erased memory cells. Here, it is possible to change theorder of the steps S241 and S242.

In step S243, it may be decided whether the verification-read operationhas passed or failed. If the verification-read operation has passed, theprocedure goes to step S244, in which the verification-read voltage Vvfymay be decreased by the offset value V_(OS). If the verification-readoperation has failed, the procedure goes to step S245, in which theverification-read voltage Vvfy may be increased by the offset valueV_(OS).

After deciding a new verification-read voltage, in step S246, it may bejudged whether the offset value V_(OS) (0.8V) is equal to or less than0.1V. If the offset value V_(OS) is judged not to be equal to or lessthan 0.1V, the procedure goes to step S241, in which a secondverification-read voltage may be executed based on a verification-readvoltage Vvfy decided in step S244/S245. For example, in the event thatthe verification-read operation is judged to have passed in step S243,the verification-read voltage Vvfy may be set to 0.8V (1.6V−0.8V). Inthe event that the verification-read operation is judged to have failedin step S243, the verification-read voltage Vvfy may be set to 2.4V(1.6V+0.8V).

In step S246, if the offset value V_(OS) is judged to be equal to orless than 0.1V, the procedure goes to step S247, in which an erasevoltage Ve may be set to (Ve+Vvfy) when a last verification-readoperation is judged to have passed or to (Ve+Vvfy+0.1V) when a lastverification-read operation is judged to have failed. Here, the Vvfy maybe an increment ΔV of the erase voltage Ve which is newly determined.Afterwards, the procedure goes to step S21.

An erase operation according to an exemplary embodiment of the inventiveconcept will be more fully described with reference to FIGS. 9 to 12.

FIGS. 9 to 12 are diagrams showing threshold voltage distributions in anerase operation according to an exemplary embodiment of the inventiveconcept. Below, an erase operation according to an exemplary embodimentof the inventive concept will be more fully described with reference toFIGS. 7 to 12.

In FIG. 9, there is illustrated a threshold voltage distribution ST oferased memory cells which experience the above-described HHI.

Referring to FIG. 1 and FIGS. 7 to 9, all memory cells may not be erasedcompletely by the first erase operation executed in step S21. In otherwords, there exist memory cells whose threshold voltages are higher than0V, in other words, a verification-read voltage (0V). For this reason,the first erase operation executed in step S21 may be judged to havefailed. In this case, in step S24, there may be executed an operation ofdeciding a new erase voltage.

Referring to FIGS. 7 to 10, in step S241, the non-volatile memory device100 may execute a first verification-read operation based on averification-read voltage Vvfy of about 1.6V. In step S242, an offsetvalue V_(OS) may be set to 0.8V which is obtained by dividing an offsetvalue by 2. It is noted that the offset value V_(OS) may be set to theverification-read voltage Vvfy (1.6V) before performing step S242. Asdescribed above, the offset value V_(OS) may be used to terminate anoperation of searching for a maximum upper voltage of a thresholdvoltage distribution of erased memory cells.

In step S243, it may be decided whether the verification-read operationhas passed or failed. Since the voltage Vvfy of 1.6V is higher than amaximum upper voltage (0.3V) (or, an upper limit voltage), theverification-read operation is judged to have passed. If theverification-read operation is judged to have passed, theverification-read voltage Vvfy may be decreased by the offset valueV_(OS). In other words, a current verification-read voltage Vvfy may beset to 0.8V (1.6V−0.8V). In step S246, it may be judged whether theoffset value V_(OS) is less than a reference voltage of 0.1V. Since theoffset value V_(OS) (0.8V) is higher than the reference voltage (0.1V),the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a secondverification-read operation based on a current verification-read voltageVvfy of 0.8V. In step S242, the offset value V_(OS) may be set to 0.4Vwhich is obtained by dividing the offset value (0.8V) by 2. In stepS243, it may be decided whether the verification-read operation haspassed or failed. Since the voltage Vvfy (0.8V) is higher than themaximum upper voltage (0.3V), the verification-read operation is judgedto have passed. If the verification-read operation is judged to havepassed, the verification-read voltage Vvfy may be decreased by theoffset value V_(OS). In other words, a current verification-read voltageVvfy may be set to 0.4V (0.8V−0.4V). In step S246, it may be judgedwhether the offset value V_(OS) is less than a reference voltage of0.1V. Since the offset value V_(OS) (0.4V) is higher than the referencevoltage (0.1V), the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a thirdverification-read operation based on a verification-read voltage Vvfy of0.4V. In step S242, the offset value V_(OS) may be set to 0.2V which isobtained by dividing the offset value (0.4V) by 2. In step S243, it maybe decided whether the verification-read operation has passed or failed.Since the voltage Vvfy (0.4V) is higher than the maximum upper voltage(0.3V), the verification-read operation is judged to have passed. If theverification-read operation is judged to have passed, theverification-read voltage Vvfy may be decreased by the offset valueV_(OS). In other words, a current verification-read voltage Vvfy may beset to 0.2V (0.4V−0.2V). In step S246, it may be judged whether theoffset value V_(OS) is less than a reference voltage of 0.1V. Since theoffset value V_(OS) (0.2V) is higher than the reference voltage (0.1V),the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a fourthverification-read operation based on a verification-read voltage Vvfy of0.2V. In step S242, the offset value V_(OS) may be set to 0.1V which isobtained by dividing the offset value V_(OS) by 2. In step S243, it maybe decided whether the verification-read operation has passed or failed.Since the voltage Vvfy (0.2V) is lower than the maximum upper voltage(0.3V), the verification-read operation is judged to have failed. If theverification-read operation is judged to have failed, theverification-read voltage Vvfy may be increased by the offset valueV_(OS) (0.1V). In other words, a current verification-read voltage Vvfymay be set to 0.3V (0.2V+0.1V). In step S246, it may be judged whetherthe offset value V_(OS) is equal to or less than a reference voltage of0.1V. Since the offset value V_(OS) (0.1V) is equal to the referencevoltage (0.1V), the procedure goes to step S247.

The verification-read voltage and the offset voltage may be summarizedas follows.

TABLE 1 Vvfy V_(OS) P/F Next Vvfy 1^(st) verify read 1.6 V 0.8 V P 0.8 V(Vvfy − V_(OS)) 2^(nd) verify read 0.8 V 0.4 V P 0.4 V (Vvfy − V_(OS))3^(rd) verify read 0.4 V 0.2 V P 0.2 V (Vvfy − V_(OS)) 4^(th) verifyread 0.2 V 0.1 V F 0.3 V (Vvfy + V_(OS))

As understood from table 1, a maximum upper voltage of a thresholdvoltage distribution ST may be searched for with the above-describedoperation. The found maximum upper voltage, in other words, a currentverification-read voltage Vvfy may be used as an increment ΔV of anerase voltage Ve. In step S247, there may be decided an erase voltage Veto be used at a next erase operation, in other words, a second eraseoperation. For example, an erase voltage Ve may be set to (Ve+Vvfy) whena last verification-read operation is judged to have passed. The erasevoltage Ve may be set to (Ve+Vvfy+0.1V) when a last verification-readoperation is judged to have failed. As illustrated in table 1, the lastverification-read operation is judged to have failed. For this reason,the increment ΔV for the second erase operation may be set to 0.4V(Vvfy+0.1V). Thus, the erase voltage Ve for the second erase operationmay be increased by 0.4V. In step S21, the second erase operation may beexecuted based on the erase voltage thus decided. In step S22, averification-read operation may be executed based on 0V. Theverification-read operation may be judged to have passed in S23. This isbecause the increment of the erase voltage Ve is set to 0.4V higher thanthe maximum upper voltage (0.3V). In other words, since thresholdvoltages of memory cells are shifted in a negative direction by 0.4V,the verification-read operation may be judged to have passed in S23.

In an exemplary embodiment, a given voltage can be added optionally tothe increment ΔV (Vvfy/Vvfy+0.1) to minimize the stress to memory cellsand to pass the erase operation.

Referring to FIGS. 1, 7, 8 and 11, all memory cells may not be erasedcompletely by the first erase operation executed in step S21. In otherwords, there exist memory cells whose threshold voltages are higher than0V, in other words, a verification-read voltage. For this reason, averification-read operation executed in step S22 may be judged to havefailed. In this case, in step S24, there may be executed an operation ofdeciding a new erase voltage.

Referring to FIGS. 7, 8, 11, and 12, in step S241, the non-volatilememory device 100 may execute a first verification-read operation basedon a maximum verification-read voltage Vvfy of 1.6V. In step S242, theoffset value V_(OS) may be set to 0.8V which is obtained by dividing anoffset value by 2. It is noted that the offset value V_(OS) may be setto the verification-read voltage Vvfy (1.6V) before performing the stepS242. In step S243, it may be decided whether the verification-readoperation has passed or failed. Since the voltage Vvfy (1.6V) is higherthan an upper voltage (0.8V), the verification-read operation is judgedto have passed. If the verification-read operation is judged to havepassed, the verification-read voltage Vvfy may be decreased by theoffset value V_(OS). In other words, a current verification-read voltageVvfy may be set to 0.8V (1.6V−0.8V). In step S246, it may be judgedwhether the offset value V_(OS) is equal to or less than a referencevoltage of 0.1V. Since the offset value V_(OS) (0.8V) is higher than thereference voltage (0.1V), the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a secondverification-read operation based on a verification-read voltage Vvfy of0.8V. In step S242, the offset value V_(OS) may be set to 0.4V which isobtained by dividing the offset value (0.8V) by 2. In step S243, it maybe decided whether the verification-read operation has passed or failed.Since the voltage Vvfy (0.8V) is equal to the upper voltage (0.8V), theverification-read operation is judged to have failed. If theverification-read operation is judged to have failed, theverification-read voltage Vvfy may be increased by the offset valueV_(OS). In other words, a current verification-read voltage Vvfy may beset to 1.2V (0.8V+0.4V). In step S246, it may be judged whether theoffset value V_(OS) is equal to or less than a reference voltage of0.1V. Since the offset value V_(OS) (0.4V) is higher than the referencevoltage (0.1V), the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a thirdverification-read operation based on a verification-read voltage Vvfy of1.2V. In step S242, the offset value V_(OS) may be set to 0.2V which isobtained by dividing the offset value (0.4V) by 2. In step S243, it maybe decided whether the verification-read operation has passed or failed.Since the voltage Vvfy (1.2V) is higher than the upper voltage (0.8V),the verification-read operation is judged to have passed. If theverification-read operation is judged to have passed, theverification-read voltage Vvfy may be decreased by the offset valueV_(OS). In other words, a current verification-read voltage Vvfy may beset to 1.0V (1.2V−0.2V). In step S246, it may be judged whether theoffset value V_(OS) is equal to or less than a reference voltage of0.1V. Since the offset value V_(OS) (0.2V) is higher than the referencevoltage (0.1V), the procedure goes to step S241.

In step S241, the non-volatile memory device 100 may execute a fourthverification-read operation based on a verification-read voltage Vvfy of1.0V. In step S242, the offset value V_(OS) may be set to 0.1V which isobtained by dividing the offset value (0.2V) by 2. In step S243, it maybe decided whether the verification-read operation has passed or failed.Since the voltage Vvfy (1.0V) is higher than the upper limit voltage(0.8V), the verification-read operation is judged to have passed. If theverification-read operation is judged to have passed, theverification-read voltage Vvfy may be decreased by the offset valueV_(OS). In other words, a current verification-read voltage Vvfy may beset to 0.9V (1.0V−0.1V). In step S246, it may be judged whether theoffset value V_(OS) is equal to or less than a reference voltage of0.1V. Since the offset value V_(OS) (0.1V) is equal to the referencevoltage (0.1V), the procedure goes to step S247.

The verification-read voltage and the offset voltage may be summarizedas follows.

TABLE 2 Vvfy V_(OS) P/F Next Vvfy 1^(st) verify read 1.6 V 0.8 V P 0.8 V(Vvfy − V_(OS)) 2^(nd) verify read 0.8 V 0.4 V F 1.2 V (Vvfy + V_(OS))3^(rd) verify read 1.2 V 0.2 V P 1.0 V (Vvfy − V_(OS)) 4^(th) verifyread 1.0 V 0.1 V P 0.9 V (Vvfy − V_(OS))

As understood from table 2, a maximum upper voltage of a thresholdvoltage distribution ST may be searched for with the above-describedoperation. The found maximum upper voltage, in other words, a currentverification-read voltage Vvfy may be used as an increment ΔV of anerase voltage Ve. In step S247, there may be decided an erase voltage Veto be used at a next erase operation, in other words, the second eraseoperation. For example, an erase voltage Ve may be set to (Ve+Vvfy) whena last verification-read operation is judged to have passed. The erasevoltage Ve may be set to (Ve+Vvfy+0.1V) when a last verification-readoperation is judged to have failed. As illustrated in table 2, the lastverification-read operation is judged to have passed. For this reason,the increment ΔV for the second erase operation may be set to 0.9V.Thus, the erase voltage Ve for the second erase operation may beincreased by 0.9V. In step S21, the second erase operation may beexecuted based on the erase voltage Ve thus decided. In step S22, averification-read operation may be executed based on 0V. Theverification-read operation may be judged to have passed in S23. This isbecause the increment of the erase voltage Ve is set to 0.9V higher thanthe maximum upper voltage (0.8V). In other words, since thresholdvoltages of memory cells are shifted in a negative direction by 0.9V,the verification-read operation may be judged to have passed in S23.

The inventive concept may be applied to search for a new read referencevoltage when errors are not recovered by the ECC engine. In other words,exemplary embodiments of the inventive concept may be applied to a readoperation since they are applied to a verification-read operation of anerase process.

A read method of a non-volatile memory device according to exemplary anembodiment of the inventive concept comprises a) reading thenon-volatile memory device with a read voltage; b) when a read result isuncorrectable by the ECC engine, performing a verification operationbased on a maximum read verification voltage; c) increasing ordecreasing the maximum read verification voltage by an offset voltageaccording to the verification result, wherein the offset voltage isobtained by dividing the maximum read verification voltage by 2; and d)performing a verification-read operation based on the thus increased ordecreased read verification voltage.

The read method further comprises generating a read voltage which ischanged by adding the maximum read verification voltage to the readvoltage when the offset voltage is less than a given value. The readmethod further comprises performing step (a) based on the changed readvoltage.

Flash memory devices are a type of nonvolatile memory capable of keepingdata stored therein even without power supply. Flash memory devices areused to store code and data in mobile apparatuses such as cellularphones, personal digital assistants (PDA), digital cameras, portablegaming consoles, and MP3 players, for example. Flash memory devices maybe also utilized in high-definition TVs, digital versatile disks (DVDs),routers, and global positioning systems (GPSs).

FIG. 13 is a block diagram showing a computing system including a flashmemory device according to an exemplary embodiment of the inventiveconcept. A computing system 10 according to the present inventiveconcept includes a processing unit 13 such as a microprocessor or a CPU,a user interface 14, a modem 16 such as a baseband chipset, a memorycontroller 12, and a flash memory device 11. The flash memory device 11may be configured like that shown FIG. 1. In the flash memory device 11,N-bit data (N is an integer of 1 or more) to be processed by theprocessing unit 13 are stored through the memory controller 12. If thecomputing system 10 shown in FIG. 13 is a mobile apparatus, it isfurther comprised of a battery 15 for supplying power thereto. Althoughnot shown in FIG. 13, the computing system 10 may be further equippedwith an application chipset, a camera image processor (e.g., a CMOSimage sensor (CIS)), and a mobile dynamic random access memory (DRAM),for example. The memory controller 12 and the flash memory device 11,for example, may be configured to form a solid state drive (SSD) whichuses non-volatile memory devices to store data. An exemplary SSD isdisclosed in commonly assigned U.S. Patent Application Publication No.2006/0152981, filed Dec. 19, 2005, the disclosure of which isincorporated by reference herein in its entirety. Alternatively, thememory controller 12 and the flash memory device 11 may be configured toform a memory card which uses non-volatile memory devices to store data.

FIG. 14 is a block diagram showing a memory-based storage deviceaccording to an exemplary embodiment of the inventive concept.

A memory-based storage device 20 in FIG. 14 may include a card 21 whichis formed of a memory 22 and a memory controller 23. For example, thecard 21 may be a memory card such as a flash memory card. In otherwords, the card 21 may be a card which satisfies a standard for use withelectronic devices such as digital cameras, and personal computers, forexample. It is to be understood that the memory controller 23 controlsthe memory 22 based on control signals sent from a host 24.

While the inventive concept has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the inventive concept as defined by the following claims.

1. An erase method of a non-volatile memory device, comprising: firsterasing memory cells of a nonvolatile memory device with a first erasevoltage; in response to a judgment that the first erasure of at leastone of the memory cells has failed, determining an amount of voltage toadd to the first erase voltage, the amount being based on a thresholdvoltage distribution of the first erased memory cells; and seconderasing the memory cells with a second erase voltage, the second erasevoltage being higher than the first erase voltage by the determinedamount.
 2. The erase method of claim 1, wherein the amount to add to thefirst erase voltage is determined by searching for a maximum uppervoltage of the threshold voltage distribution of the first erased memorycells that is less than a verification-read voltage.
 3. The erase methodof claim 2, wherein the maximum upper voltage is searched for byiteratively performing a verification-read operation.
 4. The erasemethod of claim 1, wherein the erasure of the memory cells is terminatedby applying the second erase voltage to the memory cells.
 5. The erasemethod of claim 1, wherein the memory cells to be erased are selected.6. The erase method of claim 1, wherein the memory cells comprise amulti-level cell.
 7. An erase method of a non-volatile memory device,comprising: first erasing memory cells of a non-volatile memory devicewith a first erase voltage; in response to a judgment that the firsterasure of at least one of the memory cells has failed: a) performing averification operation with a first verification-read voltage; b)obtaining an offset value by using the first verification-read voltage;c) increasing or decreasing the first verification-read voltage by theoffset value to generate a new verification-read voltage, based on aresult of the verification operation; and d) determining whether theoffset value is less than or equal to a reference voltage; and inresponse to the offset value being less than or equal to the referencevoltage, second erasing the memory cells with a second erase voltageobtained by adding the new verification-read voltage to the first erasevoltage; otherwise, repeating a-d with each newly generatedverification-read voltage as the first verification-read voltage untilthe offset value is less than or equal to the reference voltage, andthen, performing the second erasure of the memory cells.
 8. The erasemethod of claim 7, wherein the verification operation is judged to havepassed in response to the first verification-read voltage being higherthan a maximum upper voltage of a threshold voltage distribution of thefirst erased memory cells.
 9. The erase method of claim 8, wherein inresponse to the judgment that the verification operation has passed, thenew verification-read voltage is obtained by subtracting the offsetvalue from the first verification-read voltage.
 10. The erase method ofclaim 7, wherein the verification operation is judged to have failed inresponse to the first verification-read voltage being less than amaximum upper voltage of a threshold voltage distribution of the firsterased memory cells.
 11. The erase method of claim 10, wherein inresponse to the judgment that the verification operation has failed, thenew verification-read voltage is obtained by adding the offset value tothe first verification-read voltage.
 12. The erase method of claim 7,wherein the first erasure of at least one of the memory cells is judgedto have failed in response to a maximum upper voltage of a thresholdvoltage distribution of the first erased memory cells being higher thana predetermined verification-read voltage.
 13. The erase method of claim12, wherein the predetermined verification-read voltage is 0V.
 14. Theerase method of claim 12, wherein the second erase voltage is less thanthe predetermined verification-read voltage.
 15. The erase method ofclaim 7, wherein the offset value is obtained by dividing the firstverification-read voltage by a number more than one.
 16. A read methodof a non-volatile memory device comprising: first reading memory cellsof a non-volatile memory device with a first read voltage; in responseto a judgment that the first reading of at least one of the memory cellsis uncorrectable: a) performing a verification operation with a firstread verification voltage; b) obtaining an offset voltage by using thefirst read verification voltage; c) increasing or decreasing the firstread verification voltage by the offset voltage to generate a new readverification voltage, according to a result of the verificationoperation; and d) determining whether the offset voltage is less than orequal to a reference voltage; and in response to the offset voltagebeing less than or equal to the reference voltage, second reading thememory cells with a second read voltage obtained by adding the new readverification voltage to the first read voltage; otherwise, repeating a-dwith each newly generated read verification voltage as the first readverification voltage until the offset voltage is less than or equal tothe reference voltage, and then, performing the second reading of thememory cells.
 17. The read method of claim 16, wherein an error checkingand correction (ECC) algorithm determines that the reading of at leastone of the memory cells is uncorrectable.